DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 585

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.44 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 11.44 Cascaded Combinations
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Combination
Channels 1 and 2
Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
TGRC_0
TGRB_0
TGRA_0
TGRA_0
counters operates independently in phase counting mode.
H'0000
TIOCA
TCNT_0 value
Cascaded Operation
H'0200
H'0200
H'0200
Upper 16 Bits
TCNT_1
TGRC_0 to TGRA_0 Transfer Timing
H'0450
H'0450
Transfer
H'0450
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 3.00 May 17, 2007 Page 527 of 1582
Lower 16 Bits
TCNT_2
H'0520
H'0520
REJ09B0181-0300
H'0520
Time