DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 557

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Note:
Table 11.32 Setting of Bits BF1 and BF0
Table 11.33 TIOC4D Output Level Select Function
Note: The reverse phase waveform initial output value changes to the active level after elapse of
Bit
0
Bit 7
BF1
0
0
1
1
Bit 5
OLS3N
0
1
the dead time after count start.
*
Bit Name
OLS1P
Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
Initial Output
High level
Low level
Bit 6
BF0
0
1
0
1
Initial
value
0
Complementary PWM Mode
Does not transfer data from the
buffer register (TOLBR) to TOCR2.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
trough of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest and trough of the TCNT_4
count.
Active Level
Low level
High level
R/W
R/W
Description
Output Level Select 1P*
This bit selects the output level on TIOC3B in reset-
synchronized PWM mode/complementary PWM mode.
See table 11.38.
Up Count
High level
Low level
Function
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Description
Rev. 3.00 May 17, 2007 Page 499 of 1582
Compare Match Output
Reset-Synchronized PWM Mode
Does not transfer data from the
buffer register (TOLBR) to TOCR2.
Transfers data from the buffer
register (TOLBR) to TOCR2 when
TCNT_3/TCNT_4 is cleared
Setting prohibited
Setting prohibited
Down Count
Low level
High level
REJ09B0181-0300