DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 792

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 15 Serial Communication Interface (SCI)
15.3.7
SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF,
ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The
TEND flag is a read-only bit and cannot be modified.
Rev. 3.00 May 17, 2007 Page 734 of 1582
REJ09B0181-0300
Bit
7
Serial Status Register (SCSSR)
Bit Name
TDRE
Note:
*
Initial value:
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
value
1
R/W:
Bit:
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
TDRE
7
1
R/W
R/(W)* Transmit Data Register Empty
RDRF ORER
6
0
5
0
Description
Indicates whether data has been transferred from the
transmit data register (SCTDR) to the transmit shift
register (SCTSR) and SCTDR has become ready to
be written with next serial transmit data.
0: Indicates that SCTDR holds valid transmit data
[Clearing conditions]
•
•
•
1: Indicates that SCTDR does not hold valid transmit
[Setting conditions]
•
•
•
data
When 0 is written to TDRE after reading TDRE = 1
When data is written to SCTDR by a TXI interrupt
through the DMAC
When the DTC is activated by a TXI interrupt and
transmit data is transferred to SCTDR while the
DISEL bit of MRB in the DTC is 0
By a power-on reset or in standby mode
When the TE bit in SCSCR is 0
When data is transferred from SCTDR to SCTSR
and data can be written to SCTDR
FER
4
0
PER
3
0
TEND
R
2
1
MPB
R
1
0
MPBT
R/W
0
0