DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1311

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

(1) SCI Interface Setting by Host
Table 23.8 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of
Note: The internal clock division ratio of ×1/3 is not supported in boot mode.
Host Bit Rate
9,600 bps
19,200 bps
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-
communication data (H'00), which is transmitted consecutively by the host. The SCI
transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit
rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation
described above must be executed. The bit rate between the host and this LSI is not matched
because of the bit rate of transmission by the host and system clock frequency of this LSI. To
operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200
bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI is shown in table 23.8. Boot mode must be initiated in the range of this
system clock. Note that the internal clock division ratio of ×1/3 is not supported in boot mode.
This LSI
Figure 23.7 Automatic Adjustment Operation of SCI Bit Rate
Peripheral Clock (Pφ) Frequency Which Can Automatically Adjust LSI's
Bit Rate
10 to 40 MHz
10 to 40 MHz
Start
bit
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
D4
D5
Rev. 3.00 May 17, 2007 Page 1253 of 1582
D6
D7
Stop bit
High period of
at least 1 bit
Section 23 Flash Memory
REJ09B0181-0300