DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 134

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 4 Clock Pulse Generator (CPG)
Notes: *
Rev. 3.00 May 17, 2007 Page 76 of 1582
REJ09B0181-0300
1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1,
2. The output frequency of the PLL circuit is the product of the frequency of the input from
3. The input to the divider is always the output from the PLL circuit.
4. The internal clock (Iφ) frequency is the product of the frequency of the input from the
5. The bus clock (Bφ) frequency is the product of the frequency of the input from the
6. The peripheral clock (Pφ) frequency is the product of the frequency of the input from the
7. When using the MTU2S and MTU2, the MTU2S clock (MIφ) frequency must be equal to
8. The frequency of the CK pin is always be equal to the bus clock (Bφ) frequency.
Clock frequencies when the input clock frequency is assumed to be the shown value.
×1/2, ×1/3, ×1/4, and ×1/8 for each clock by the setting in the frequency control register.
the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit.
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 80 MHz
(maximum operating frequency).
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and
equal to or lower than the internal clock (Iφ) frequency.
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and
equal to or lower than the bus clock (Bφ) frequency.
or lower than the internal clock (Iφ) frequency and equal to or higher than the MTU2
clock (MPφ) frequency. The MTU2 clock (MPφ) frequency must be equal to or lower
than the MTU2S clock (MIφ) frequency and the bus clock (Bφ) frequency and equal to
or higher than the peripheral clock frequency (Pφ). The MTU2S clock (MIφ) frequency
and MTU2 clock (MPφ) frequency are the product of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider.