DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 488

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.1 shows a block diagram of the MTU2.
Rev. 3.00 May 17, 2007 Page 430 of 1582
REJ09B0181-0300
Internal clock:
External clock: TCLKA
Channel 3: TIOC3A
Channel 4: TIOC4A
Channel 0: TIOC0A
Channel 1: TIOC1A
Channel 2: TIOC2A
Channel 5: TIC5U
Input/output pins
Input/output pins
Clock input
Input pins
MPφ/1024
[Legend]
TSTR: Timer start register
TSYR: Timer synchronous register
TCR:
TMDR: Timer mode register
TIOR:
TIORH: Timer I/O control register H
TIORL: Timer I/O control register L
TIER:
TGCR: Timer gate control register
TOER: Timer output master enable register
TOCR: Timer output control register
TSR:
TCNT: Timer counter
TCNTS: Timer subcounter
MPφ/256
TIOC3C
TIOC3D
TIOC4C
TIOC4D
TIOC3B
TIOC4B
TIOC0C
TIOC0D
TIOC0B
TIOC1B
TIOC2B
MPφ/16
MPφ/64
TIC5W
TCLKB
TCLKC
TCLKD
TIC5V
MPφ/1
MPφ/4
Timer control register
Timer I/O control register
Timer interrupt enable register
Timer status register
Figure 11.1 Block Diagram of MTU2
TCDR:
TCBR:
TDDR:
TGRA:
TGRB:
TGRC:
TGRD:
TGRE:
TGRF:
TGRU:
TGRV:
TGRW: Timer general register W
Timer cycle buffer register
Timer general register F
Timer cycle data register
Timer dead time data register
Timer general register A
Timer general register B
Timer general register C
Timer general register D
Timer general register E
Timer general register U
Timer general register V
Interrupt request signals
Interrupt request signals
A/D conversion start signals
Channels 0 to 4: TRGAN
Channel 0:
Channel 4:
Internal data bus
Channel 5: TGIU_5
Channel 3: TGIA_3
Channel 4: TGIA_4
Channel 0: TGIA_0
Channel 1: TGIA_1
Channel 2: TGIA_2
TGIW_5
TGIC_3
TGID_3
TGIC_4
TGID_4
TGIB_3
TCIV_3
TGIB_4
TCIV_4
TGIV_5
TGIB_0
TGIC_0
TGID_0
TGIE_0
TGIB_1
TCIU_1
TGIB_2
TCIU_2
TGIF_0
TCIV_0
TCIV_1
TCIV_2
TRG4BN
TRG0N
TRG4AN