DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 48

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Table 5.10
Table 5.11
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Section 7 User Break Controller (UBC)
Table 7.1
Table 7.2
Table 7.3
Section 8 Data Transfer Controller (DTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
Table 8.9
Table 8.10
Table 8.11
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Rev. 3.00 May 17, 2007 Page xlviii of Iviii
Calculating Exception Handling Vector Table Addresses...................................... 90
Reset Status............................................................................................................. 91
Bus Cycles and Address Errors............................................................................... 93
Interrupt Sources..................................................................................................... 95
Interrupt Priority ..................................................................................................... 96
Types of Exceptions Triggered by Instructions ...................................................... 97
Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions .............. 99
Stack Status after Exception Handling Ends......................................................... 100
Pin Configuration.................................................................................................. 107
Register Configuration.......................................................................................... 108
Interrupt Exception Handling Vectors and Priorities............................................ 124
Interrupt Response Time....................................................................................... 131
Pin Configuration.................................................................................................. 137
Register Configuration.......................................................................................... 138
Data Access Cycle Addresses and Operand Size Comparison Conditions........... 160
Register Configuration.......................................................................................... 173
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 186
DTC Transfer Modes ............................................................................................ 189
DTC Transfer Conditions (Chain Transfer Conditions Included) ........................ 191
Transfer Information Writeback Skip Condition and Writeback Skipped
Registers ............................................................................................................... 195
Register Function in Normal Transfer Mode........................................................ 195
Register Function in Repeat Transfer Mode ......................................................... 197
Register Function in Block Transfer Mode........................................................... 198
DTC Execution Status .......................................................................................... 204
Number of Cycles Required for Each Execution State ......................................... 205
DTC Bus Release Timing ..................................................................................... 207
Pin Configuration.................................................................................................. 220
Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode....................................................................................................... 222
Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM-
Disabled Mode...................................................................................................... 223
Address Map: SH7083 (512-Kbyte Flash Memory Version) in On-Chip ROM-
Enabled Mode....................................................................................................... 224