DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1308

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 23 Flash Memory
23.4.4
When the realtime programming of the user MAT is emulated, RAMER sets the area of the user
MAT which is overlapped with a part of the on-chip RAM. The RAM emulation must be executed
in user mode or in user program mode.
For the division method of the user-MAT area, see table 23.7. In order to operate the emulation
function certainly, the target MAT of the RAM emulation must not be accessed immediately after
RAMER is programmed. If it is accessed, the normal access is not guaranteed.
Initial value:
Rev. 3.00 May 17, 2007 Page 1250 of 1582
REJ09B0181-0300
Bit
15 to 4 
3
2 to 0
R/W:
Bit:
Bit Name
RAMS
RAM[2:0]
RAM Emulation Register (RAMER)
15
R
0
-
14
R
0
-
13
Initial
Value
All 0
0
000
R
0
-
12
R
0
-
11
R
0
-
R/W
R
R/W
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
RAM Select
Sets whether the user MAT is emulated or not. When
RAMS = 1, all blocks of the user MAT are in the
programming/erasing protection state.
0: Emulation is not selected
1: Emulation is selected
User MAT Area Select
These bits are used with bit 3 to select the user-MAT
area to be overlapped with the on-chip RAM. (See table
23.7.)
R
9
0
-
Programming/erasing protection of all user-MAT
blocks is invalid
Programming/erasing protection of all user-MAT
blocks is valid
R
8
0
-
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
RAMS
R/W
3
0
R/W
2
0
RAM[2:0]
R/W
1
0
R/W
0
0