DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 972

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.3.5
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
Rev. 3.00 May 17, 2007 Page 914 of 1582
REJ09B0181-0300
Bit
7
6
I
2
Bit Name
TDRE
TEND
2
C Bus Status Register (ICSR)
C Bus Interface 2 (I
Initial value:
Initial
Value
0
0
R/W:
Bit:
2
C2)
TDRE
R/W
7
0
R/W
R/W
R/W
TEND
R/W
6
0
Description
Transmit Data Register Empty
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
•
Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
•
RDRF NACKF STOP AL/OVE
R/W
5
0
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
When 0 is written to TDRE after reading TDRE = 1
When data is written to ICDRT
DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clock synchronous serial format
When 0 is written to TEND after reading TEND = 1
When data is written to ICDRT
DTC is activated by IITXI interrupt and the DISEL bit
in MRB of DTC is 0.
R/W
4
0
R/W
3
0
R/W
2
0
R/W
AAS
1
0
R/W
ADZ
0
0
2
C bus