DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 306

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Note:
Rev. 3.00 May 17, 2007 Page 248 of 1582
REJ09B0181-0300
Bit
10, 9
8 to 0
*
Bit Name
BSZ[1:0]

When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0
and MD1 external pins that specify the bus width when a power-on reset is performed.
Initial
Value
11*
All 0
R/W
R/W
R
Data Bus Size Specification
Description
Specify the data bus sizes of spaces.
00: Setting prohibited
01: 8-bit size
10: 16-bit size
11: 32-bit size
Notes: 1. When MPX-I/O is selected for area 5, setting
Reserved
These bits are always read as 0. The write value should
always be 0.
Bus width determined by the address when
MPX-I/O is used
2. When the on-chip ROM is disabled, the data
3. When burst MPX-I/O is selected for area 6,
4. When PCMCIA is selected for area 5 or 6, 8-
5. When SDRAM is selected for area 2 or 3,
these bits to 11 enables the bus width (8 bits
or 16 bits) to be determined by the address
according to the SZSEL bit setting in
CS5WCR.
bus width in area 0 is specified through
external input pins. The BSZ1 and BSZ0 bit
setting in CS0BCR is ignored.
only 32-bit size can be selected for the bus
width.
bit or 16-bit size can be selected for the bus
width.
16-bit or 32-bit size can be selected for the
bus width.