DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 155

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.5
5.5.1
Exception handling can be triggered by the trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9
Note:
5.5.2
When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The CPU reads the start address of the exception handling routine from the exception handling
Type
Trap instruction
Illegal slot
instructions*
General illegal
instructions*
instruction to be executed after the TRAPA instruction.
vector table that corresponds to the vector number specified in the TRAPA instruction,
program execution branches to that address, and then the program starts. This branch is not a
delayed branch.
*
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Trap Instructions
The operation is not guaranteed when undefined instructions other than H'F000 to
H'FFFF are decoded.
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that changes the PC
value
Undefined code anywhere
besides in a delay slot
Comment

Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that changes the PC value: JMP,
JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, LDC Rm,SR,
LDC.L @Rm+,SR

Rev. 3.00 May 17, 2007 Page 97 of 1582
Section 5 Exception Handling
REJ09B0181-0300