DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 21

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.1 Features.............................................................................................................................. 901
18.2 Input/Output Pins ............................................................................................................... 904
18.3 Register Descriptions ......................................................................................................... 905
18.4 Operation ........................................................................................................................... 920
18.5 I
18.6 Operation Using the DTC .................................................................................................. 940
18.7 Bit Synchronous Circuit..................................................................................................... 941
18.8 Usage Note......................................................................................................................... 943
Section 19 A/D Converter (ADC)......................................................................945
19.1 Features.............................................................................................................................. 945
19.2 Input/Output Pins ............................................................................................................... 947
19.3 Register Descriptions ......................................................................................................... 948
18.3.1 I
18.3.2 I
18.3.3 I
18.3.4 I
18.3.5 I
18.3.6 I
18.3.7 I
18.3.8 I
18.3.9 I
18.3.10 NF2CYC Register (NF2CYC) .............................................................................. 919
18.4.1 I
18.4.2 Master Transmit Operation ................................................................................... 921
18.4.3 Master Receive Operation..................................................................................... 923
18.4.4 Slave Transmit Operation ..................................................................................... 926
18.4.5 Slave Receive Operation....................................................................................... 929
18.4.6 Clock Synchronous Serial Format ........................................................................ 930
18.4.7 Noise Filter ........................................................................................................... 934
18.4.8 Example of Use..................................................................................................... 935
18.8.1 Module Standby Mode Setting ............................................................................. 943
18.8.2 Issuance of Stop Condition and Repeated Start Condition ................................... 943
18.8.3 Issuance of a Start Condition and Stop Condition in Sequence ............................ 943
18.8.4 Settings for Multi-Master Operation..................................................................... 944
18.8.5 Reading ICDRR in Master Receive Mode............................................................ 944
19.3.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) .............................................. 949
19.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2)........................ 950
19.3.3 A/D Control Registers_0 to _2 (ADCR_0 to ADCR_2)....................................... 953
2
C2 Interrupt Sources........................................................................................................ 939
2
2
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1)..................................................................... 905
C Bus Control Register 2 (ICCR2)..................................................................... 908
C Bus Mode Register (ICMR)............................................................................ 910
C Bus Interrupt Enable Register (ICIER) ........................................................... 912
C Bus Status Register (ICSR)............................................................................. 914
C Bus Slave Address Register (SAR)................................................................. 917
C Bus Transmit Data Register (ICDRT)............................................................. 918
C Bus Receive Data Register (ICDRR).............................................................. 918
C Bus Shift Register (ICDRS)............................................................................ 918
C Bus Format...................................................................................................... 920
C Bus Interface 2 (I
2
C2) ................................................................901
Rev. 3.00 May 17, 2007 Page xxi of lviii