DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 343

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.5
9.5.1
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM
with byte selection, and two data bus widths (16 bits and 32 bits) are available for SDRAM. For
PCMCIA interface, two data bus widths (8 bits and 16 bits) are available. For MPX-I/O, the data
bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. For
burst MPX-I/O, the data bus width is fixed at 32 bits. Data alignment is performed in accordance
with the data bus width of the respective device. This also means that when longword data is read
from a byte-width device, the read operation must be done four times. In this LSI, data alignment
and conversion of data length are performed automatically between the respective interfaces.
Tables 9.17 to 9.19 show the relationship between device data width and access unit.
Table 9.17 32-Bit External Device Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword access
at 0
Operation
Endian/Access Size and Data Alignment
D31 to
D24
Data 7 to
Data 0



Data 15 to
Data 8

Data 31 to
Data 24
D23 to
D16

Data 7 to
Data 0


Data 7 to
Data 0

Data 23 to
Data 16
Data Bus
D15 to
D8


Data 7 to
Data 0


Data 15 to
Data 8
Data 15 to
Data 8
D7 to
D0



Data 7 to
Data 0

Data 7 to
Data 0
Data 7 to
Data 0
Rev. 3.00 May 17, 2007 Page 285 of 1582
WRHH,
DQMUU
Assert



Assert

Assert
Section 9 Bus State Controller (BSC)
WRHL,
DQMUL

Assert


Assert

Assert
Strobe Signals
WRH,
DQMLU


Assert


Assert
Assert
REJ09B0181-0300
WRL,
DQMLL



Assert

Assert
Assert