DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 921

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.3.1
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit
7
6
5
Bit Name
MSS
BIDE

SS Control Register H (SSCRH)
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
R/W
MSS
R/W
R/W
R/W
R
7
0
BIDE
R/W
6
0
Description
Master/Slave Device Select
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
17.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
1: Bidirectional mode (one pin is used for data input and
Reserved
This bit is always read as 0. The write value should
always be 0.
R
5
0
-
output)
output)
Section 17 Synchronous Serial Communication Unit (SSU)
R/W
SOL
4
0
SOLP
R/W
3
1
Rev. 3.00 May 17, 2007 Page 863 of 1582
R
2
1
-
R/W
1
0
CSS[1:0]
R/W
0
1
REJ09B0181-0300