DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 390

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
2. Self-refreshing
Rev. 3.00 May 17, 2007 Page 332 of 1582
REJ09B0181-0300
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses
are generated within SDRAM. Self-refreshing is activated by setting both the RMODE bit and
the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in the
Tp cycle after the completion of the precharging bank. A SELF command is then issued after
inserting idle cycles of which number is specified by the WTRP[1:0] bits in CS3WCR.
SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by
clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is
disabled for the number of cycles specified by the WTRC[1:0] bits in CS3WCR.
Self-refresh timing is shown in figure 9.29. After self-refreshing is cleared, settings must be
made so that auto-refreshing is performed at the correct intervals. When self-refreshing is
activated from the state in which auto-refreshing is set, auto-refreshing is restarted if the RFSH
bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the
transition from clearing of self-refresh mode to the start of auto-refreshing takes time, making
the RTCNT value 1 less than the RTCOR value will enable auto-refreshing to be started
immediately.
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
Notes: 1.
DQMxx
RDWR
CSn
CK
BS
1
2
2.
Address pin to be connected to pin A10 of SDRAM.
The waveform for DACKn is when active low is specified.
Figure 9.28 Auto-Refresh Timing
Tp
Tpw
Trr
Hi-z
Trc
Trc
Trc