DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 954

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 Synchronous Serial Communication Unit (SSU)
(4)
Figure 17.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Rev. 3.00 May 17, 2007 Page 896 of 1582
REJ09B0181-0300
Note: Hatching boxes represent SSU internal operations.
[1]
[2]
[4]
[5]
Data Transmission/Reception
No
Read received data in SSRDR
Read receive data in SSRDR
RDRF automatically cleared
Overrun error processing
Consecutive data reception?
Clear ORER in SSSR
End reception
End reception
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
RE = 0
Start
Figure 17.16 Flowchart Example of Data Reception
Yes
Yes
No
(Clock Synchronous Communication Mode)
Yes
No
[3]
[1]
[2]
[3], [5] Receive error processing:
[4]
Initial setting:
Specify the receive data format.
Start reception:
When setting the RE bit to 1, reception is started.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.