DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 28

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
Figure 6.1 Block Diagram of INTC............................................................................................ 106
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................. 122
Figure 6.3 Interrupt Sequence Flowchart ................................................................................... 129
Figure 6.4 Stack after Interrupt Exception Handling.................................................................. 130
Figure 6.5 IRQ Interrupt Control Block Diagram ...................................................................... 132
Figure 6.6 On-Chip Module Interrupt Control Block Diagram .................................................. 133
Section 7 User Break Controller (UBC)
Figure 7.1 Block Diagram of UBC............................................................................................. 136
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 172
Figure 8.2 Transfer Information on Data Area ........................................................................... 185
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information............... 185
Figure 8.4 Flowchart of DTC Operation .................................................................................... 190
Figure 8.5 Transfer Information Read Skip Timing
Figure 8.6 Memory Map in Normal Transfer Mode................................................................... 196
Figure 8.7 Memory Map in Repeat Transfer Mode
Figure 8.8 Memory Map in Block Transfer Mode
Figure 8.9 Operation of Chain Transfer...................................................................................... 200
Figure 8.10 Example of DTC Operation Timing:
Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2
Figure 8.12 Example of DTC Operation Timing: Chain Transfer
Rev. 3.00 May 17, 2007 Page xxviii of Iviii
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 States).............................................................. 194
(When Transfer Source is Specified as Repeat Area)................................................ 197
(When Transfer Destination is Specified as Block Area).......................................... 199
Normal Transfer Mode or Repeat Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles) .......................................................... 201
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles) .......................................................... 201
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles) .......................................................... 202