DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 414

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.5.11
The burst-ROM (clock synchronous) interface provides high-speed access to ROM that has a
synchronous burst function. Access through this interface is basically performed in the same way
as access to the normal space. If this interface is used, it must be placed in area 0.
For the first access cycle, the number of wait cycles specified by the W3 to W0 bits in CS0WCR
are inserted. For the second and subsequent access cycles, the number of wait cycles specified by
the BW1 and BW0 bits in CS0WCR are inserted (0 to 3 cycles). In access to the burst ROM
(clock synchronous), the BS signal is only asserted on the first access cycle. Furthermore, an
external wait input is only valid for the first access cycle.
Set burst length = 8 when the bus width is 16 bits and burst length = 4 when the bus width is 32
bits. The 8-bit bus width is not supported. All read access through this interface is in burst mode.
For example, in accessing a longword when the bus width is 16 bits, the data from the first two
read operations are valid but unnecessary data is read out in the next six dummy operations. This
dummy reading slows down memory access rate, lengthening program-execution and DMA-
transfer times. Avoiding this requires the effective use of 16-byte DMA transfer.
Rev. 3.00 May 17, 2007 Page 356 of 1582
REJ09B0181-0300
D15 to D0
DACKn*
Address
RDWR
Note: * The waveform for DACKn is when active low is specified.
WAIT
(Burst Length = 8, Access Wait for the 1st time = 2, Access Wait for 2nd Time after = 1)
CS0
RD
CK
BS
T1
Burst ROM (Clock Synchronous) Interface
Tw
Figure 9.48 Burst ROM (Clock Synchronous) Access Timing
Tw
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2