DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 216

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.4
7.4.1
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses are set in the break address registers (BARA or BARB). The masked
2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
4. There is a chance that matches of the break conditions set in channels A and B occur almost at
5. When selecting the I bus as the break condition, note the following:
Rev. 3.00 May 17, 2007 Page 158 of 1582
REJ09B0181-0300
addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is
set in the break data register (BDRA or BDRB). The masked data is set in the break data mask
register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle
registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select,
instruction fetch/data access select, and read/write select) are each set. No user break will be
generated if even one of these groups is set with B'00. The respective conditions are set in the
bits of the break control register (BRCR). Make sure to set all registers related to breaks before
setting BBRA or BBRB.
CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition
match flag (SCMFDA or SCMFDB) for the appropriate channel.
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. Before using them again, 0 must first be written to them and then reset
flags.
the same time. In this case, there will be only one user break request to the CPU, but these two
conditions match flags could be both set.
 The CPU, DMAC, and DTC are connected to the I bus. The UBC monitors bus cycles
 I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by
 The DMAC and DTC only issue data access cycles for I bus cycles.
 If a break condition is specified for the I bus, even when the condition matches in an I bus
generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the
CPB2 to CPB0 bits in BBRB, and compares the conditions for a match.
the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are
defined as data access cycles.
cycle resulting from an instruction executed by the CPU, at which instruction the user
break is to be accepted cannot be clearly defined.
Operation
Flow of the User Break Operation