DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 978

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 I
18.4
The I
by setting FS in SAR.
18.4.1
Figure 18.3 shows the I
following a start condition always consists of eight bits.
[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
Rev. 3.00 May 17, 2007 Page 920 of 1582
REJ09B0181-0300
(a) I
(b) I
S
1
S
1
2
2
2
C bus interface 2 can communicate either in I
C bus format (FS = 0)
C bus format (Start condition retransmission, FS = 0)
Slave address
Stop condition. The master device drives SDA from low to high while SCL is high.
Start condition. The master device drives SDA from high to low while SCL is high.
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receive device drives SDA to low.
SDA
SCL
Operation
I
SLA
SLA
2
2
C Bus Format
7
7
C Bus Interface 2 (I
S
1
1
R/W
R/W
1
1
SLA
1-7
2
C bus formats. Figure 18.4 shows the I
A
A
1
1
R/W
8
2
C2)
DATA
DATA
n1
n
Figure 18.3 I
Figure 18.4 I
9
A
m1
A
1
A/A
m
1
1-7
DATA
2
S
1
C Bus Formats
2
C Bus Timing
2
8
C bus mode or clock synchronous serial mode
SLA
A/A
1
7
A
9
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
P
1
1
2
R/W
C bus timing. The first frame
1
1-7
DATA
A
1
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
8
DATA
n2
9
A
m2
P
A/A
1
1
P