EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1003

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–13. MegaWizard Plug-In Manager Options (Rate Match/Byte Order Screen) (Part 2 of 3)
February 2011 Altera Corporation
Create the rx_rmfifoempty port to
indicate when the rate match FIFO is
empty.
Create the
rx_rmfifodatainserted port to
indicate when data is inserted in the
rate match FIFO.
Create the rx_rmfifodatadeleted
port to indicate when data is deleted
in the rate match FIFO.
Enable insertion or deletion of
consecutive characters or ordered
sets
Enable byte ordering block.
What do you want the byte ordering
to be based on?
What is the byte ordering pattern?
ALTGX Setting
This option creates the output port rx_rmfifoempty
when you enable the Enable Rate Match FIFO option.
It is a status flag that the rate match block forwards
to the FPGA fabric. It indicates when the rate match
FIFO block is empty (5 words full). This signal
remains high as long as the FIFO is empty. It is
asynchronous to the receiver data path.
This option creates the output port
rx_rmfifodatainserted flag when you enable the
Enable Rate Match FIFO option. It is a status flag
that the rate match block forwards to the FPGA fabric.
This indicates the insertion of skip patterns. For every
deletion, this signal is high for one parallel clock
cycle.
This option creates the output port
rx_rmfifodatadeleted flag when you enable the
Enable Rate Match FIFO option. It is a status flag
that the rate match block forwards to the FPGA fabric.
This indicates the deletion of skip patterns. For every
insertion, this signal is high for one parallel clock
cycle.
This option enables the back-to-back insertion or
deletion of skip characters in the rate match FIFO.
This option is available for selection in Single-width
mode. It is enabled by default in Double-width mode.
This option enables the byte ordering block. It is
available in both Single-width and Double-width
modes. It is available only when the channel width is:
■
■
As soon as the byte ordering block sees the rising
edge of the appropriate signal, it compares the
LSByte coming out of the byte deserializer with the
byte ordering pattern. If they do not match, the byte
ordering block inserts the pad character that you
enter in the What is the byte ordering pad pattern?
option such that the byte ordering pattern is seen in
the LSByte position. Inserting this pad character
enables the byte ordering block to restore the correct
byte order.
This option is available only when the byte ordering
block is enabled. This option allows you to trigger the
byte ordering block on the rising edge of either the
rx_syncstatus signal or the user-controlled
rx_enabyteord signal from the FPGA fabric.
This option is available only when the byte ordering
block is enabled. Enter the 10-bit pattern that the byte
ordering block must place in the LSByte position of
the receiver parallel data on the rx_dataout port.
16-bits/20-bits in Single-width mode
32-bits/40-bits in Double-width mode
Description
Stratix IV Device Handbook Volume 3
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture In Stratix IV
Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture in Stratix IV
Devices
“Rate Match FIFO in Basic
Single-Width Mode” and
“Rate Match FIFO in Basic
Double-Width Mode”
sections in the
Architecture in Stratix IV
Devices
“Byte Ordering Block”
section in the
Architecture in Stratix IV
Devices
“Byte Ordering Block”
section in the
Architecture In Stratix IV
Devices
“Byte Ordering Block”
section in the
Architecture in Stratix IV
Devices
chapter.
chapter.
chapter.
chapter.
chapter.
chapter.
Reference
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Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
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