EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 200

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

6–28
Stratix IV Device Handbook Volume 1
On-Chip Parallel Termination with Calibration
Stratix IV devices support on-chip parallel termination with calibration in all banks.
On-chip parallel termination with calibration is only supported for input
configuration of input and bidirectional pins. Output pin configurations do not
support on-chip parallel termination with calibration.
parallel termination with calibration. When you use parallel OCT, the V
bank must match the I/O standard of the pin where the parallel OCT is enabled.
Figure 6–20. On-Chip Parallel Termination with Calibration
The on-chip parallel termination calibration circuit compares the total impedance of
the I/O buffer to the external 50- Ω ±1% resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
with calibration.
Table 6–7. Selectable I/O Standards with On-Chip Parallel Termination with Calibration
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
Differential SSTL-2 Class I, II
Differential SSTL-18 Class I, II
Differential SSTL-15 Class I, II
Differential HSTL-18 Class I, II
Differential HSTL-15 Class I, II
Differential HSTL-12 Class I, II
Table 6–7
I/O Standard
Transmitter
lists the I/O standards that support on-chip parallel termination
Termination Setting
Z
O
On-Chip Parallel
(Column I/O) (Ω)
= 50 Ω
On-Chip Termination Support and I/O Termination Schemes
50
50
50
50
50
50
50
50
50
50
50
50
V
REF
Chapter 6: I/O Features in Stratix IV Devices
Figure 6–20
V
CCIO
GND
100 Ω
100 Ω
Stratix IV OCT
February 2011 Altera Corporation
Receiver
Termination Setting
On-Chip Parallel
shows on-chip
(Row I/O) (Ω)
50
50
50
50
50
50
50
50
50
50
50
50
CCIO
of the