EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 721

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–13. Receiver Datapath Clock Frequencies PCIe x8 Functional Mode
February 2011 Altera Corporation
PCIe ×8 (Gen 1)
PCIe ×8 (Gen 2)
Functional Mode
1
The CDR in each of the eight receiver channels recovers the serial clock from the
received data on that channel. The serial recovered clock is divided within each
channel’s receiver PMA to generate the parallel recovered clock. The deserializer uses
the serial recovered clock in the receiver PMA. The parallel recovered clock and
deserialized data from the receiver PMA in each channel is forwarded to the receiver
PCS in that channel.
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and the write side of the rate matcher FIFO in that channel. The low-speed
parallel clock from the CMU0 clock divider of the master transceiver block clocks the
read port of the rate match FIFO, the 8B/10B decoder, and the write port of the byte
deserializer (if enabled) in all eight channels. The low-speed parallel clock or its
divide-by-two version (if byte deserializer is enabled) clocks the write port of the
receiver phase compensation FIFO in all eight channels. It is also driven on the
coreclkout port as the FPGA fabric-Transceiver interface clock. You can use the
coreclkout signal to latch the receiver data and status signals in the FPGA fabric for
all eight bonded channels.
Table 2–13
Basic (PMA Direct) Mode Channel Configurations
Figure 2–28
Direct) functional mode with two of the channels being CMU channels. The receiver
channel PMA directly interfaces to the user logic in the FPGA fabric. The CDR
recovers the high-speed serial clock and low-speed parallel clock for the deserializer.
The low-speed parallel clock is forwarded to the FPGA fabric as rx_clkout.
Bonded mode is not available for receivers configured in Basic (PMA Direct)
functional mode. Data registers to capture the receiver data in the FPGA fabric for
each channel must be clocked by rx_clkout forwarded by that channel’s CDR.
Data Rate
(Gbps)
2.5
5
lists the receiver datapath clock frequencies in PCIe ×8 functional mode.
shows six channels in a transceiver block configured in Basic (PMA
Serial Recovered
Clock Frequency
(GHz)
1.25
2.5
Transmitter PCS Clock
Parallel Recovered
Clock and Parallel
Frequency (MHz)
250
500
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA Fabric-Transceiver
(MHz)
250
N/A
Deserializer
With Byte
(MHz)
125
250
2–49