EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 422

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

12–4
I/O Voltage Support in a JTAG Chain
BST Circuitry
BSDL Support
Stratix IV Device Handbook Volume 1
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The JTAG chain supports several devices. However, you must use caution if the chain
contains devices that have different V
For more information, refer to the
Stratix III Devices
The IEEE Std. 1149.1 BST circuitry is enabled after device power-up. You can perform
BST on Stratix IV devices before, during, and after configuration. Stratix IV devices
support BYPASS, IDCODE, and SAMPLE JTAG instructions during configuration without
interrupting configuration. To send all other JTAG instructions, you must interrupt
configuration using the CONFIG_IO JTAG instruction.
For more information, refer to
Altera
For more information about using the CONFIG_IO JTAG instruction for dynamic I/O
buffer configuration, considerations when performing BST for configured devices,
and JTAG pin connections to mask-out the BST circuitry, refer to the
(JTAG) Boundary-Scan Testing in Stratix III Devices
Device Handbook.
For more information about using the IEEE Std.1149.1 circuitry for device
configuration, refer to the
Stratix IV Devices
If you must perform BST for configured devices, you must use the Quartus II software
version 8.1 and onwards to generate the design-specific boundary-scan description
language (BSDL) files. For the procedure to generate post-configured BSDL files using
the Quartus II software, refer to the
website.
BSDL, a subset of VHDL, provides a syntax that allows you to describe the features of
an IEEE Std. 1149.1 BST-capable device that can be tested.
For more information about BSDL files for IEEE Std. 1149.1-compliant Stratix IV
devices, refer to the
BSDL files for IEEE std. 1149.1-compliant Stratix IV devices can also be generated
using the Quartus II software version 8.1 and onwards. For more information about
the procedure to generate BSDL files using the Quartus II software, refer to the
Files Generation in Quartus II
Devices.
chapter in volume 1 of the Stratix III Device Handbook.
chapter.
Stratix IV BSDL Files
Configuration, Design Security, Remote System Upgrades in
on the Altera website.
AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
IEEE 1149.1 (JTAG) Boundary-Scan Testing in
BSDL Files Generation in Quartus II
CCIO
Chapter 12: JTAG Boundary-Scan Testing in Stratix IV Devices
on the Altera website.
levels.
chapter in volume 1 of the Stratix III
I/O Voltage Support in a JTAG Chain
February 2011 Altera Corporation
IEEE 1149.1
on the Altera
BSDL