EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 268

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

7–48
Figure 7–29. Stratix IV Read-Leveling Delay Chains and Multiplexers
Notes to
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have one memory interface in each
(2) Each divider feeds up to six pins (from a × 4 DQS group) in the device. To feed wider DQS groups, you must chain multiple clock dividers together
Stratix IV Device Handbook Volume 1
I/O sub-bank when you use the leveling delay chain.
by feeding the slaveout output of one divider to the masterin input of the neighboring pins’ divider.
Resynchronization Clock
(resync_clk_2x)
Figure
DQS
7–29:
Figure 7–28
Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers
Note to
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have
The –90° write clock of the ALTMEMPHY megafunction feeds the write-leveling
circuitry to produce the clock to generate the DQS and DQ signals. During
initialization, the ALTMEMPHY megafunction picks the correct write-leveled clock
for the DQS and DQ clocks for each DQS/DQ group after sweeping all the available
clocks in the write calibration process. The DQ clock output is –90° phase-shifted
compared to the DQS clock output.
Similarly, the resynchronization clock feeds the read-leveling circuitry to produce the
optimal resynchronization and postamble clock for each DQS/DQ group in the
calibration process. The resynchronization and postamble clocks can use different
clock outputs from the leveling circuitry. The output from the read-leveling circuitry
can also generate the half-rate resynchronization clock that goes to the FPGA fabric.
one memory interface in each I/O sub-bank when you use the leveling delay chain.
Figure
7–28:
and
Write clk
delayctrlin
6
(-90
Figure 7–29
0
)
phasectrlin
show the Stratix IV write- and read-leveling circuitry.
4
0111
0110
0101
0100
0011
0010
0001
0000
phaseinvertctrl
0
1
Chapter 7: External Memory Interfaces in Stratix IV Devices
(Note 1)
masterin
Read-Leveled Resynchronization Clock
I/O Clock Divider (2)
use_masterin
1
0
Write-Leveled DQ Clock
Write-Leveled DQS Clock
Stratix IV External Memory Interface Features
DFF
phaseselect
slaveout
1
0
February 2011 Altera Corporation
clkout
(Note 1)
Half-Rate
Resynchronization Clock
Half-Rate Source
Synchronous Clock