EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 273

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
Delay Chain
The output path is designed to route combinatorial or registered SDR outputs and
full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to
full-rate using the HDR block, clocked by the half-rate clock from the PLL. The
resynchronization registers are also clocked by the same 0° system clock, except in the
DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling registers are
clocked by the write-leveling clock.
For more information about the write-leveling delay chain, refer to
Circuitry” on page
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the
DQS logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output.
Figure 7–33. Delay Chain
Every I/O block contains the following:
■
■
■
■
Two delay chains in a series between the output registers and the output buffer
One delay chain between the input buffer and the input register
Two delay chains between the output enable and the output buffer
Two delay chains between the OCT R
buffer
datain
7–47.
delayctrlin [3..0]
Figure 7–33
Δt
shows the delay chain ports.
T
enable control register and the output
finedelayctrlin
Δt
<use finedelayctrlin>
Stratix IV Device Handbook Volume 1
0
1
dataout
“Leveling
7–53