EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 149

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
Post-Scale Counter Cascading
1
Each PLL has one pre-scale counter, n, and one multiply counter, m, with a range of
1 to 512 for both m and n. The n counter does not use duty-cycle control because the
only purpose of this counter is to calculate frequency division. There are seven generic
post-scale counters per left or right PLL and ten post-scale counters per top or bottom
PLL that can feed the GCLKs, RCLKs, or external clock outputs. These post-scale
counters range from 1 to 512 with a 50% duty cycle setting. The high- and low-count
values for each counter range from 1 to 256. The sum of the high- and low-count
values chosen for a design selects the divide value for a given counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
Stratix IV PLLs support post-scale counter cascading to create counters larger than
512. This is automatically implemented in the Quartus II software by feeding the
output of one C counter into the input of the next C counter, as shown in
Figure 5–30. Counter Cascading
Note to
(1) N = 6 or N = 9
When cascading post-scale counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter with the
product of the individual counter settings. For example, if C0 = 40 and C1 = 20, the
cascaded value is C0 × C1 = 800.
Post-scale counter cascading is set in the configuration file. You cannot set this using
PLL reconfiguration.
Figure
5–30:
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
C0
C1
C2
C3
C4
Cn
(1)
from preceding
post-scale counter
Stratix IV Device Handbook Volume 1
Figure
5–30.
5–33