EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 138

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–22
Stratix IV Device Handbook Volume 1
Stratix IV PLL Hardware Overview
Stratix IV devices contain up to 12 PLLs with advanced clock management features.
The goal of a PLL is to synchronize the phase and frequency of an internal or external
clock to an input reference clock. There are a number of components that comprise a
PLL to achieve this phase alignment.
Stratix IV PLLs align the rising edge of the input reference clock to a feedback clock
using the phase-frequency detector (PFD). The falling edges are determined by the
duty-cycle specifications. The PFD produces an up or down signal that determines
whether the VCO must operate at a higher or lower frequency. The output of the PFD
feeds the charge pump and loop filter, which produces a control voltage for setting the
VCO frequency. If the PFD produces an up signal, the VCO frequency increases. A
down signal decreases the VCO frequency. The PFD outputs these up and down
signals to a charge pump. If the charge pump receives an up signal, current is driven
into the loop filter. Conversely, if the charge pump receives a down signal, current is
drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is used to bias the
VCO. The loop filter also removes glitches from the charge pump and prevents
voltage over-shoot, which filters the jitter on the VCO. The voltage from the loop filter
determines how fast the VCO operates. A divide counter (m) is inserted in the
feedback loop to increase the VCO frequency above the input reference frequency.
VCO frequency (f
reference clock (f
pre-scale counter (N). Therefore, the feedback clock (f
PFD is locked to the f
The VCO output from the left and right PLLs can feed seven post-scale counters
(C[0..6]), while the corresponding VCO output from the top and bottom PLLs can
feed ten post-scale counters (C[0..9]). These post-scale counters allow a number of
harmonically related frequencies to be produced by the PLL.
R EF
VCO
) to the PFD is equal to the input clock (f
) is equal to (m) times the input reference clock (f
REF
that is applied to the other input of the PFD.
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
FB
) applied to one input of the
IN
February 2011 Altera Corporation
) divided by the
PLLs in Stratix IV Devices
R EF
). The input