EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 534

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–90
Figure 1–77. 8B/10B Decoder in Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
The 8B/10B decoder operates in single-width mode in the following functional
modes:
■
■
■
■
■
For PCIe, XAUI, GIGE, and Serial RapidIO functional modes, the ALTGX
MegaWizard Plug-In Manager forces selection of the 8B/10B decoder in the receiver
datapath. In Basic single-width mode, it allows you to enable or disable the 8B/10B
decoder depending on your proprietary protocol implementation.
Figure 1–77
identifier by the 8B/10B decoder in single-width mode.
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or
control code group on the rx_ctrldetect port. If the received 10-bit code group is one
of the 12 control code groups (/Kx.y/) specified in the IEEE802.3 specification, the
rx_ctrldetect signal is driven high. If the received 10-bit code group is a data code
group (/Dx.y/), the rx_ctrldetect signal is driven low.
Figure 1–78
code group into an 8-bit data code group (8'hBC) driven on the rx_dataout port. The
rx_ctrldetect signal is asserted high synchronous with 8'hBC on the rx_dataout
port, indicating that it is a control code group. The rest of the codes received are data
code groups /Dx.y/.
PCIe
XAUI
GIGE
Serial RapidIO
Basic single-width
MSB Received Last
Control Code Group Detection
ctrl
shows a 10-bit code group decoded into an 8-bit data and a 1-bit control
shows the 8B/10B decoder decoding the received 10-bit /K28.5/ control
9
j
h
8
H
7
g
7
G
6
6
8B/10B Conversion
f
5
F
5
i
E
4
e
4
3
D
d
3
2
C
c
2
B
Chapter 1: Transceiver Architecture in Stratix IV Devices
1
LSB Received First
b
1
0
A
Parallel Data
a
0
February 2011 Altera Corporation
Transceiver Block Architecture