EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 919

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–37. Enabling EyeQ Mode
February 2011 Altera Corporation
reconfig_mode_sel[3:0]
ctrl_writedata[15:0]
ctrl_readdata[15:0]
ctrl_address[15:0]
ctrl_waitrequest
Adaptive Equalization (AEQ)
reconfig_clk
ctrl_write
ctrl_read
busy
6. Poll the EyeQ interface register 0×0 (the control and status register) and wait for
7. If the next operation is to the same EyeQ register and same channel, you do not
Example of Using the EyeQ Feature
Consider a design with one regular transceiver channel configured in Basic functional
mode. The channel has a data rate of 2.5 Gbps with the EyeQ feature enabled in both
the ALTGX and ALTGX_RECONFIG instances.
mode is first enabled by writing into the EyeQ registers using the EyeQ interface
registers. A phase step value of 25 is written to the EyeQ register. Before performing
any operation, the following conditions must be met:
■
■
High-speed interface systems require different equalization settings to compensate for
changing data rates and backplane losses. Manual tuning of the receiver channel’s
equalization stages involves finding the optimal settings through trial and error, and
then locking in those values at compile time. This manual method is cumbersome
under varying system characteristics. The AEQ feature solves this problem by
automatically tuning an active receiver channel’s equalization filters based on a
frequency content comparison between the incoming signal and internally generated
reference signals.
the busy status to be de-asserted. After the status is no longer busy, the data is
considered successfully written for write transactions. For read transactions, this
indicates that the contents of the data register has been updated and can be read
out. Note that all writes that occur when the busy status is asserted are ignored;
all registers become read only.
need to repeat steps 2 and 3.
busy is 0 in the EyeQ CSR
ctrl_waitrequest is low
0
0
x
4’b1011
1
4
Enable EyeQ
2
0
1
3
…
…
…
…
0
Figure 5–37
Stratix IV Device Handbook Volume 2: Transceivers
Set EyeQ Phase Step Value to 25
0
2
shows how the EyeQ
25
3
1
0
5–73