EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 669

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Reference Information
February 2011 Altera Corporation
Table 1–80. Reference Information (Part 2 of 3)
Programmable Differential On-Chip Termination
Offset Cancellation in the Receiver Buffer and
Rate Match (Clock Rate Compensation) FIFO
Programmable Equalization and DC Gain
Programmable Common Mode Voltage
Transmitter Local Clock Divider Block
Signal Threshold Detection Circuitry
Receiver Phase Compensation FIFO
Reverse serial Pre-CDR Loopback
PCIe Reverse Parallel Loopback
Transceiver Channel Locations
Transceiver Block Architecture
Transmitter Polarity Inversion
TX Phase Compensation FIFO
Programmable Pre-Emphasis
Terms Used in this Chapter
Deterministic Latency Mode
PCIe Clock Switch Circuitry
Low Latency PCS Datapath
Receiver Polarity Inversion
Transmitter Output Buffer
Lock-to-Reference (LTR)
Reverse Serial Loopback
Transmitter Bit Reversal
SATA and SAS options
Transceiver Port Lists
Receiver Bit Reversal
Receiver Input Buffer
Serial RapidIO Mode
Lock-to-Data (LTD)
SONET/SDH Mode
Parallel loopback
CPRI and OBSAI
Serial Loopback
Receiver CDR
Deskew FIFO
Deserializer
GIGE Mode
PCIe Mode
SDI Mode
EyeQ
Stratix IV Device Handbook Volume 2: Transceivers
Useful Reference Points
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