EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 566

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–122
Figure 1–102. Transceiver Datapath When in Deterministic Latency Mode
Stratix IV Device Handbook Volume 2: Transceivers
FPGA
Fabric
Deterministic Latency Mode
Stratix IV GX and GT devices have a deterministic latency option available for use in
high-speed serial interfaces such as CPRI (Common Public Radio Interface) and Open
Base Station Architecture Initiative Reference Point3 (OBSAI RP3). Both CPRI and
OBSAI RP3 protocols place stringent requirements on the amount of latency variation
that is permissible through a link implementing these protocols.
Figure 1–102
To implement this mode, select the Deterministic Latency option under the Which
Protocol will you be using? section in the ALTGX MegaWizard Plug-In Manager.
When you select this option, the transmitter channel is automatically placed in bit-slip
mode and Enable TX Phase Comp FIFO in register mode is automatically selected as
well. The receiver ’s phase compensation FIFO is automatically placed in the register
mode. In addition, an output port (rx_bitslipboundaryselectout[4:0]) from the
receiver’s word aligner and an input port (tx_bitslipboundaryselect[4:0]) for the
transmitter bit-slip circuitry are instantiated. The option for placing the transmitter
phase compensation FIFO in register mode is also available.
Transmitter Bit Slipping
The transmitter is bit slipped to achieve deterministic latency. Use the
tx_bitslipboundaryselect[4:0] port to set the number of bits that the transmitter
block needs to slip.
under different channel widths.
Table 1–44. Number of Transmitter Bits Allowed to be Slipped in Deterministic Latency Mode
Compensation
wrclk
TX Phase
shows the transceiver datapath when using deterministic latency mode.
FIFO
Channel Width
rdclk
16/20 bit
8/10 bit
Table 1–44
Byte Serializer
wrclk
Receiver Channel PCS
Transmitter Channel PCS
lists the number of bits that are allowed to be slipped
rdclk
Transmitter Channel Datapath
Receiver Channel Datapath
Chapter 1: Transceiver Architecture in Stratix IV Devices
8B/10B Encoder
Slip Zero
February 2011 Altera Corporation
19 bits
9 bits
Transceiver Block Architecture
Transmitter Channel
Receiver Channel
PMA
PMA