EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 320

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

8–42
Stratix IV Device Handbook Volume 1
Guidelines for DPA-Disabled Differential Channels
f
1
When you use DPA-disabled channels in the left and right banks of a Stratix IV
device, you must adhere to the guidelines in the following sections.
When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices
DPA-Disabled Channels and Single-Ended I/Os
The placement rules for DPA-disabled channels and single-ended I/Os are the same
as those for DPA-enabled channels and single-ended I/Os. For more information,
refer to
DPA-Disabled Channel Driving Distance
Each left and right PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center Left and Right PLLs
You can use a corner left and right PLL to drive all transmitter channels and a center
left and right PLL to drive all DPA-disabled receiver channels within the same
differential bank. In other words, a transmitter channel and a receiver channel in the
same LAB row can be driven by two different PLLs, as shown in
A corner left and right PLL and a center left and right PLL can drive duplex channels
in the same differential bank, as long as the channels driven by each PLL are not
interleaved. Separation is not necessary between the group of channels driven by the
corner and center left and right PLLs, as shown in
“DPA-Enabled Channels and Single-Ended I/Os” on page
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
chapter.
Figure 8–34
Differential Pin Placement Guidelines
February 2011 Altera Corporation
and
Figure
8–38.
Figure
8–34.
8–35.