EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 803

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combination Requirements for Stratix IV Devices
Combination Requirements for Stratix IV Devices
Summary
February 2011 Altera Corporation
Placement Rules for Transceiver Channels at 9.9 Gbps to 11.3 Gbps
Stratix IV GT devices allow configuring multiple protocols or data rates in the same
transceiver block. For common protocols supported by both Stratix IV GX and GT
devices, as well as for Basic functional mode at data rates between 2.488 Gbps and
8.5 Gbps, Stratix IV GT devices follow the same transceiver channel placement rules
as Stratix IV GX devices.
You can use either the CMU PLL or the 10G ATX PLL to generate transceiver clocks
for channels configured at data rates between 9.9 Gbps and 10.3125 Gbps.
If you use a 10G ATX PLL to generate transceiver clocks for any channel configured
between 9.9 Gbps and 10.3125 Gbps within a transceiver block, the remaining
channels in the same transceiver block must either be unused or must be configured
at the same data rate and clocked by the same 10G ATX PLL.
If you use a CMU PLL to generate transceiver clocks for any channel configured
between 8.5 Gbps and 11.3 Gbps within a transceiver block, the remaining channels in
the same transceiver block may be configured at a different data rate and clocked by
another CMU PLL or 6G ATX PLL. In this case, Stratix IV GT devices follow the same
transceiver channel placement rules as Stratix IV GX devices.
Placing transceiver channels clocked by another PLL in the same transceiver block as
a 10G channel can result in higher transmitter output jitter on the 10G channel. The
amount of additional jitter is pending characterization.
The following is a summary for configuring multiple protocols and data rates in a
transceiver block:
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■
■
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You can run each transceiver channel at independent data rates or in independent
protocol functional modes.
Each transceiver block consists of two CMU PLLs that provide clocks to run the
transmitter channels within the transceiver block.
To enable the Quartus II software to combine multiple instances of transceiver
channels within a transceiver block, follow the rules specified in
Requirements to Combine Channels” on page 3–3
page
You can reset each CMU PLL within a transceiver block using a pll_powerdown
signal. For each transceiver instance, the ALTGX MegaWizard Plug-In Manager
provides an option to select the pll_powerdown port. If you want to share the same
CMU PLL between multiple transceiver channels, connect the pll_powerdown
ports of the instances and drive the signal from the same logic.
3–5.
Stratix IV Device Handbook Volume 2: Transceivers
and
“Sharing CMU PLLs” on
“General
3–49