EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 624

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–180
Figure 1–146. SDI Mode Datapath
Stratix IV Device Handbook Volume 2: Transceivers
1
1
tx_coreclk
rx_coreclk
Fabric
FPGA
FPGA Fabric-Transmitter
SDI Mode Datapath
Figure 1–146
The transmitter datapath, in HD-SDI configuration with 10-bit wide FPGA
fabric-transceiver interface, consists of the transmitter phase compensation FIFO and
the 10:1 serializer. The transmitter datapath, in HD-SDI and 3G-SDI configurations
with 20-bit wide FPGA fabric-transceiver interface, also includes the byte serializer.
In SDI mode, the transmitter is purely a parallel-to-serial converter. SDI transmitter
functions, such as scrambling and cyclic redundancy check (CRC) code generation,
must be implemented in the FPGA logic array.
In the 10-bit channel width SDI configuration, the receiver datapath is comprised of
the clock recovery unit (CRU), 1:10 deserializer, word aligner in bit-slip mode, and
receiver phase compensation FIFO. In the 20-bit channel width SDI configuration, the
receiver datapath also includes the byte deserializer.
SDI receiver functions, such as de-scrambling, framing, and CRC checker, must be
implemented in the FPGA logic array.
In SDI systems, the word aligner in the receiver datapath is not useful because word
alignment and framing happens after de-scrambling. Altera recommends driving the
ALTGX megafunction rx_bitslip signal low to avoid having the word aligner insert
bits in the received data stream.
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Transmitter Datapath
Receiver Datapath
Receiver Word Alignment and Framing
shows the transceiver datapath when configured in SDI mode.
Compensation
tx_clkout
rx_clkout
RX Phase
FIFO
Compensation
wrclk
TX Phase
FIFO
rdclk
Transmitter Channel PCS
wrclk
Byte De-
serializer
Serializer
/2
Receiver Channel PCS
Byte
/2
rdclk
Low-Speed Parallel Clock
Recovered Clock
Parallel
Chapter 1: Transceiver Architecture in Stratix IV Devices
Word
Aligner
Serializer
Transmitter Channel PMA
Receiver Channel PMA
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed
Serial Clock
Transceiver Block Architecture