EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 976

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–18
Table 1–3. MegaWizard Plug-In Manager Options (Ports/Calibration Screen) (Part 2 of 3)
Stratix IV Device Handbook Volume 3
Create a
tx_phase_comp_fifo_error output
port.
Create an rx_coreclk port to connect
to the read clock of the RX phase
compensation FIFO.
Create a tx_coreclk port to connect
to the write clock of the TX phase
compensation FIFO.
Create a tx_forceelecidle input
port
Use calibration block.
ALTGX Setting
This output port indicates a
Transmitter Phase Compensation
FIFO overflow or under-run
condition.
You can clock the parallel output data
from the receiver using this optional
input port. This port allows you to
clock the read side of the Receiver
Phase Compensation FIFO with a
user-provided clock (FPGA fabric
clock, FPGA fabric-Transceiver
interface clock, or input reference
clock).
You can clock the parallel transmitter
data generated in the FPGA fabric
using this optional input port. This
port allows you to clock the write
side of the Transmitter Phase
Compensation FIFO with a
user-provided clock (FPGA fabric
clock, FPGA fabric-Transceiver
interface clock, or input reference
clock).
In Basic and PCIe modes, this
optional input signal places the
transmitter buffer in the electrical
idle state.
The calibration block is always
enabled.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“TX Phase Compensation FIFO Status
Signal” section in the
Architecture in Stratix IV Devices
“FPGA Fabric-Transceiver Interface
Clocking” section in the
Clocking in Stratix IV Devices
“FPGA Fabric-Transceiver Interface
Clocking” section in the
Clocking in Stratix IV Devices
“Transceiver Channel Architecture” section
in the
Devices
“Calibration Blocks” section in the
Transceiver Architecture in Stratix IV
Devices
Transceiver Architecture in Stratix IV
chapter.
chapter.
February 2011 Altera Corporation
Reference
Transceiver
Transceiver
Transceiver
Parameter Settings
chapter.
chapter.
chapter.