EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 178

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

6–6
Figure 6–1. Stratix IV E Devices I/0 Banks
Notes to
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/Os are powered by V
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8)
Stratix IV Device Handbook Volume 1
inverted.
single-ended clock inputs. All outputs use the corresponding bank V
Figure 6–1
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Bank 3A
6–1:
Bank 8A
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 3B
Bank 8B
SSTL-15 Class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations.
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I, and differential HSTL -12
Class I standards for input and output operations.
LVPECL I/O standard for input operation on dedicated
clock input pins.
CCCLKIN
(Note
Bank 3C
when configured as differential clock inputs. They are powered by V
Bank 8C
1), (2), (3), (4), (5), (6), (7),
CCIO
.
Bank 7C
Bank 4C
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 4B
(8)
Bank 7B
Chapter 6: I/O Features in Stratix IV Devices
February 2011 Altera Corporation
Bank 4A
Bank 7A
CCIO
when configured as
I/O Banks