EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 347

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
Table 10–4. FPP Timing Parameters for Stratix IV Devices (Part 2 of 2)
April 2011 Altera Corporation
t
t
t
T
t
t
t
t
t
t
t
f
Notes to
(1) This information is preliminary.
(2) Use these timing parameters when you have not enabled the decompression and design security features.
(3) You can obtain this value if you do not delay the configuration by extending the nCONFIG or nSTATUS low pulse width.
(4) This value is applicable if you do not delay the configuration by externally holding nSTATUS low.
(5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting the device.
(6) Adding up t
(7) Applicable to EP4SE230, EP4SE360, EP4SGX70, EP4SGX110, EP4SGX180, EP4SGX230, EP4SGX290 (except F45 package), EP4SGX360 (except
(8) Applicable to EP4SE530, EP4SGX290 (only for F45 package), EP4SGX360 (only for F45 package), EP4SGX530, EP4S40G5, EP4S100G3,
(9) Applicable to EP4SE820 only.
Symbol
ST2CK
DSU
DH
CD2UM
CD2CU
CD2UMC
CH
CL
CLK
MAX
R
F45 package), EP4S40G2, EP4S100G2 devices.
EP4S100G4, EP4S100G5 devices.
Table
nSTATUS high to first rising
edge of DCLK
Data setup time before
rising edge on DCLK
Data hold time after rising
edge on DCLK
Input rise time
Input fall time
CONF_DONE high to user
mode
CONF_DONE high to CLKUSR
enabled
CONF_DONE high to user
mode with CLKUSR option
on
DCLK high time
DCLK low time
DCLK period
DCLK frequency
10–4:
CH
and t
(5)
Parameter
CL
equals to t
(6)
(6)
(6)
CLK
. When EP4SE230 t
Stratix IV
3.6
3.6
(7)
8
t
CD2CU
CH
is 3.6 ns (min), t
4 × maximum
DCLK period
+ (8532 × CLKUSR
Minimum
Stratix IV
period)
4.5
4.5
—
—
55
10
—
(8)
2
4
1
CL
Stratix IV
must be 4.4 ns and vice versa.
12.5
5.6
5.6
(9)
(Note
1),
Stratix IV
125
(7)
(2)
Stratix IV Device Handbook Volume 1
Maximum
Stratix IV
150
100
(8)
—
—
—
40
40
—
—
—
—
—
Stratix IV
(9)
80
10–13
Units
MHz
μs
μs
—
—
ns
ns
ns
ns
ns
ns
ns