EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 995

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–11. MegaWizard Plug-In Manager Options (8B10B Screen) (Part 3 of 3)
February 2011 Altera Corporation
Enable transmitter bit reversal.
Create a tx_invpolarity
port to allow Transmitter
polarity inversion.
Create tx_bitslipboundary
select port to control the
number of words slipped in
the TX bitslipper.
ALTGX Setting
Enabling this option in:
■
■
For example, if the 8-bit parallel data at the input of the
serializer is '00111101', enabling this option reverses
this serializer input data to '10111100.'
This optional port allows you to dynamically reverse
the polarity of every bit of the data word fed to the
serializer in the transmitter data path. Use this option
when the positive and negative signals of the
differential output from the transmitter (tx_dataout)
are erroneously swapped on the board.
You can only select this option when you use the
Transmitter only or Receiver and Transmitter
operation mode. This option enables the
tx_bitslipboundaryselect input to control the
number of bits slipped in the TX bitslipper.
Single-width mode—the 8-bit D[7:0] or 10-bit
D[9:0] data at the input of the serializer gets
rewired to D[0:7] or D[0:9], respectively.
Double-width mode—the 16-bit D[15:0] or 20-bit
D[19:0] data at the input of the serializer gets
rewired to D[0:15] or D[0:19], respectively.
Description
“Transmitter Bit Reversal” section
in the
Stratix IV Devices
“Transmitter Polarity Inversion”
section in the
Architecture in Stratix IV Devices
chapter.
Stratix IV Device Handbook Volume 3
Transceiver Architecture in
Reference
Transceiver
—
chapter.
1–37