EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 120

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–4
Figure 5–2. RCLK Networks (EP4SE230, EP4SGX70, and EP4SGX110 Devices)
Note to
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
Stratix IV Device Handbook Volume 1
another four core signals can drive into RCLK[54..63] at any one time.
Figure
Regional Clock Networks
5–2:
RCLK networks only pertain to the quadrant they drive into. RCLK networks provide
the lowest clock delay and skew for logic contained within a single device quadrant.
The Stratix IV device IOEs and internal logic within a given quadrant can also drive
RCLKs to create internally generated regional clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–2
drive the RCLK networks in Stratix IV devices.
CLK[0..3]
through
L2
RCLK[0..5]
RCLK[6..11]
Figure 5–4 on page 5–5
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
CLK[12..15]
Q1
Q4
CLK[4..7]
T1
B1
Q2
Q3
RCLK[38..43]
RCLK[32..37]
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
show the CLK pins and PLLs that can
(Note 1)
R2
CLK[8..11]
Clock Networks in Stratix IV Devices
February 2011 Altera Corporation