EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 359

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
Passive Serial Configuration
April 2011 Altera Corporation
Guidelines for Connecting Serial Configuration Devices on an AS Interface
f
f
1
You can program a serial configuration device in-system by an external
microprocessor using SRunner. SRunner is a software driver developed for embedded
serial configuration device programming, which can be easily customized to fit in
different embedded systems. SRunner is able to read raw programming data (.rpd)
and write to serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming time with the
Quartus II software.
For more information about SRunner, refer to
for Serial Configuration Device Programming
at www.altera.com.
For more information about programming serial configuration devices, refer to the
Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and the Stratix IV device family
must follow the recommendations listed in
Table 10–6. Maximum Trace Length and Loading for the AS Configuration
You can program a PS configuration for Stratix IV devices using an intelligent host,
such as a MAX II device or microprocessor with flash memory, or a download cable.
In the PS scheme, an external host (a MAX II device, embedded processor, or host PC)
controls configuration. Configuration data is clocked into the target Stratix IV device
using the DATA0 pin at each rising edge of DCLK.
The Stratix IV decompression and design security features are fully available when
configuring your Stratix IV device using PS mode.
DCLK
DATA[0]
nCSO
ASDO
Stratix IV Device AS Pins
Maximum Board Trace Length
from the Stratix IV Device to
the Serial Configuration
Device (Inches)
10
10
10
10
and the source code on the Altera website
Table
AN 418: SRunner: An Embedded Solution
10–6.
Stratix IV Device Handbook Volume 1
Maximum Board Load (pF)
15
30
30
30
10–25