EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 602

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–158
Figure 1–125. XGMII-To-PCS Code Conversion in XAUI Mode
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–125:
tx_code_group<39:0>
XGMII-To-PCS Code Conversion at the Transmitter
In XAUI mode, the 8B/10B encoder in the Stratix IV GX and GT transmitter datapath
is controlled by a transmitter state machine that maps various 8-bit XGMII codes to
10-bit PCS code groups. This state machine complies with the IEEE P802.3ae PCS
transmit source state diagram shown in
tx_code_group<39:0>
PUDR
PUDR
next_ifg = A_CNT≠0
SEND_RANDOM_Q
A
Q_det
Q_det
IF TX=||T|| THEN cvtx_terminate
SEND_Q
cod_set=1
PUDR
A_CNT≠0 *
cod_sel=1
tx_code_group<39:0>
⇐
⇐
!reset
!(TX=||IDLE|| + TX=||Q||
B
FALSE
tx_code_group<39:0>
PUDR
K
Q_det
ENCODE(TX)
⇐
cod_set=1
UCT
⇐
SEND_Q
TQMSG
tx_code_group<39:0>
TQMSG
next_ifg
A
SEND_RANDOM_R
SEND_A
Q_det
A_CNT=0
⇐
K
⇐
!Q_det
tx_code_group<39:0>
⇐
PUDR
B
(next_ifg + A_CNT≠0)
||A||
SEND_RANDOM_A
⇐
||R||
A_CNT≠0 *
cod_sel=1
A
(Note 1)
!Q_det *
cod_set=1
⇐
B
A_CNT=0
||A||
Figure
!Q_det *
cod_sel=1
Chapter 1: Transceiver Architecture in Stratix IV Devices
tx_code_group<39:0>
tx_code_group<39:0>
PUDR
PUDR
SEND_RANDOM_K
UCT
1–125.
next_ifg
SEND_K
A
A
B
⇐
A
A_CNT≠0 *
cod_sel=1
reset
⇐
⇐
B
||K||
||K||
A_CNT≠0 *
cod_sel=1
February 2011 Altera Corporation
Transceiver Block Architecture