EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 843

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Dynamic Reconfiguration Reset Sequences
February 2011 Altera Corporation
Reset Sequence when Using Dynamic Reconfiguration with the ‘Channel
and TX PLL select/reconfig’ Option
Use the example reset sequence shown in
dynamic reconfiguration controller to change the TX PLL settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the data rate of the transceiver channel configured in Basic ×1 mode with
receiver CDR in automatic lock mode.
Figure 4–21. Reset Sequence When Using the Dynamic Reconfiguration Controller to Change the
TX PLL Settings of the Transceiver Channel
Note to
(1) For t
As shown in
change the configuration of the transceiver channel, follow these reset steps:
1. After power up and establishing that the transceiver is operating as desired, write
2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. Wait for the assertion of the channel_reconfig_done signal (marker 4) that
the desired new value in the appropriate registers (including
reconfig_mode_sel[2:0]) and subsequently assert the write_all signal
(marker 1) to initiate the dynamic reconfiguration.
f
execute its operation. This is indicated by the assertion of the busy signal
(marker 2).
indicates the completion of dynamic reconfiguration in this mode.
Reset and Control Signals
Figure
reconfig_mode_sel[2:0]
LTD_Auto
channel_reconfig_done
Ouput Status Signals
For more information, refer to the
Devices
4–21:
rx_analogreset
rx_digitalreset
tx_digitalreset
rx_freqlocked
duration, refer to the
Figure
write_all
busy
chapter.
4–21, when using the dynamic reconfiguration controller to
New value
1
1
1
1
DC and Switching Characteristics for Stratix IV Devices
2
3
Figure 4–21
Dynamic Reconfiguration in Stratix IV
4
Five parallel clock cycles
5
Stratix IV Device Handbook Volume 2: Transceivers
6
7
t
LTD_Auto (1)
when you are using the
8
chapter.
4–37