EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 190

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

6–18
Figure 6–17. IOE Structure in Stratix IV Devices
Notes to
(1) The D3_0 and D3_1 delays have the same available settings in the Quartus
(2) One dynamic OCT control is available per DQ/DQS group.
(3) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
Stratix IV Device Handbook Volume 1
Firm Core
DQS
CQn
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
clkin
Figure
4
6–17:
4
D4 Delay
2
Rate Block
Half Data
Rate Block
Half Data
Rate Block
Half Data
■
■
■
■
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE paths.
Figure 6–17
On-chip series termination without calibration
On-chip parallel termination with calibration
On-chip differential termination
PCI clamping diode
Delay
D3_1
Synchronization
Alignment and
Registers
Alignment
Alignment
Registers
Registers
shows the Stratix IV IOE structure.
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
Q
Q
Q
Q
(Note
1), (2),
Delay
Delay
D3_0
D1
Input Register
Input Register
D
D
PRN
PRN
(3)
D5, D6
Delay
®
Q
Q
D2 Delay
II software.
Programmable
Input Register
Strength and
D
Slew Rate
Current
Control
PRN
Q
Open Drain
D5, D6
Delay
Chapter 6: I/O Features in Stratix IV Devices
Output Buffer
Input Buffer
PCI Clamp
DQS Logic Block
February 2011 Altera Corporation
V CCIO
D5_OCT
Dynamic OCT Control (2)
V CCIO
Pull-Up Resistor
Programmable
Termination
Calibration
From OCT
On-Chip
Bus-Hold
Block
D6_OCT
Circuit
I/O Structure