EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 660

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–216
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 5 of 7)
Stratix IV Device Handbook Volume 2: Transceivers
rx_runningdisp
Byte Ordering Block
rx_enabyteord
rx_
byteorderalignstatus
Receiver Phase Compensation FIFO
rx_dataout
rx_clkout
Port Name
Output
Output
Output
Output
Output
Input/
Input
coreclkout for
coreclkout for
coreclkout for
Synchronous to
Synchronous to
Synchronous to
rx_clkout or
rx_clkout or
rx_clkout or
rx_clkout for
bonded modes
rx_clkout for
bonded modes
rx_clkout for
bonded modes
Asynchronous
Clock Domain
coreclkout.
coreclkout.
coreclkout.
non-bonded
non-bonded
non-bonded
Clock signal
modes.
modes.
modes.
signal
8B/10B running disparity indicator.
■
■
■
■
Enable byte ordering control.
■
■
Byte ordering status indicator.
■
■
Parallel data output from the receiver to the
FPGA fabric.
■
Recovered clock from the receiver channel.
■
Available in configurations with the 8B/10B
decoder.
A high level—the data on the rx_dataout
port was received with a negative running
disparity.
A low level—the data on the rx_dataout
port was received with a positive running
disparity.
Channel Width:
8—rx_runningdisp = 1
16—rx_runningdisp = 2
32—rx_runningdisp = 4
Available in configurations with the byte
ordering block enabled. The byte ordering
block is rising-edge sensitive to this signal.
A low-to-high transition triggers the byte
ordering block to restart the byte ordering
operation.
Available in configurations with the byte
ordering block enabled.
A high level—the byte ordering block has
detected the programmed byte ordering
pattern in the LSByte of the received data
from the byte deserializer.
The bus width depends on the channel width
multiplied by the number of channels per
instance.
Available only when the rate match FIFO is
not used in the receiver datapath.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Channel
Channel
Scope