EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 652

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–208
Table 1–71. Available PRBS, High Frequency, and Low Frequency Patterns in Single-Width Mode
Table 1–72. Available PRBS, High Frequency, and Low Frequency Patterns in Double-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
Patterns
Low
Frequency
Notes to
(1) Channel width refers to the What is the channel width? option in the General screen of the ALTGX MegaWizard Plug-In Manager. Based on the
(2) A verifier is not available for the specified patterns.
Patterns
PRBS 7
PRBS 23
High
frequency
Low
Frequency
Notes to
(1) Channel width refers to the what is the channel width? option in the General screen of the ALTGX MegaWizard Plug-In Manager. Based on the
(2) Verifier is not available for the specified patterns.
(2)
(2)
(2)
selection, an 8 or 10 bits wide pattern is generated as indicated by a Yes (Y) or No (N).
selection, A 16 or 20 bits wide pattern is generated as indicated by a Yes (Y) or No (N).
Table
Table
PRBS in Double-Width Mode
1–71:
1–72:
Polynomial
Polynomial
0000011111
X
1010101010
0000011111
X
23
7
+ X
+ X
The status signals rx_bistdone and rx_bisterr indicate the status of the verifier. The
rx_bistdone port gets asserted and stays high when the verifier either receives one
full cycle of incremental pattern or it detects an error in the receiver data. The
rx_bisterr signal gets asserted and stays high when the verifier detects an error. You
can reset the PRBS pattern generator and verifier by asserting the tx_digitalreset
and rx_digitalreset signals, respectively.
Table 1–72
patterns for PRBS in double-width mode configuration.
The status signals rx_bisterr and rx_bistdone are available to indicate the status of
the verifier. For more information about the behavior of these status signals, refer to
“Single-Width Mode” on page
6
18
+ 1
+ 1
16-Bit
Width of
Width of
8 Bit
Channel
Channel
lists the various PRBS patterns and corresponding word alignment
N
Y
Y
Y
N
(1)
(1)
Pattern with
Pattern with
32’h007FFFF
Width 8 Bit
Alignment
Alignment
16’h3040
Width of
Channel
Channel
16-Bit
Word
Word
NA
NA
NA
F
1–21.
16-Bit (Gbps)
Width 8 Bit
Data Rate
Maximum
Data Rate
Maximum
Width of
Channel
Channel
(Gbps)
with
With
N/A
N/A
5
5
5
Chapter 1: Transceiver Architecture in Stratix IV Devices
20-Bit
10 Bit
Width of
Width of
Channel
Channel
Y
Y
Y
Y
Y
(1)
(1)
40’h00007FF
February 2011 Altera Corporation
20’h43040
Alignment
Alignment
Pattern
Pattern
Word
Word
N/A
N/A
FFF
NA
Built-In Self Test Modes
20-Bit (Gbps)
Width 10 Bit
Data Rate
Data Rate
Maximum
Maximum
Width of
Channel
Channel
(Gbps)
6.375
6.375
6.375
6.375
3.125
with
with