EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 585

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
During link training, the upstream and downstream PCIe ports negotiate the speed
(2.5 Gbps or 5 Gbps) at which the link operates. Because the upstream and
downstream PCIe ports do not know the speed capabilities of their link partner, the
PCIe protocol requires each port to start with a Gen1 (2.5 Gbps) signaling rate. One of
the ports capable of supporting the Gen2 (5 Gbps) signaling rate might initiate a
speed change request by entering the Recovery state of the LTSSM. In the Recovery
state, each port advertises its speed capabilities by transmitting training sequences as
specified in the PCIe Base Specification 2.0. If both ports are capable of operating at
the Gen2 (5 Gbps) signaling rate, the PHY-MAC layer instructs the physical layer
device to operate at the Gen2 (5 Gbps) signaling rate.
To support speed negotiation during link training, the PCIe specification requires a
PCIe-compliant physical layer device to provide an input signal (Rate) to the
PHY-MAC layer. When this input signal is driven low, the physical layer device must
operate at the Gen1 (2.5 Gbps) signaling rate; when driven high, this input signal
must operate at the Gen2 (5 Gbps) signaling rate. The PCIe specification allows the
PHY-MAC layer to initiate a signaling rateswitch only in power states P0 and P1 with
the transmitter buffer in the Electrical Idle state. The PCIe specification allows the
physical layer device to implement the signaling rateswitch using either of the
following approaches:
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■
When configured in PCIe functional mode at Gen2 (5 Gbps) data rate, the ALTGX
MegaWizard Plug-In Manager provides the input signal rateswitch. The rateswitch
signal is functionally equivalent to the Rate signal specified in the PCIe specification.
The PHY-MAC layer can use the rateswitch signal to instruct the Stratix IV GX and
GT device to operate at either Gen1 (2.5 Gbps) or Gen2 (5 Gbps) data rate, depending
on the negotiated speed between the upstream and downstream ports. A low-to-high
transition on the rateswitch signal initiates a data rateswitch from Gen1 (2.5 Gbps) to
Gen2 (5 Gbps). A high-to-low transition on the rateswitch signal initiates a data
rateswitch from Gen2 (5 Gbps) to Gen1 (2.5 Gbps). The signaling rateswitch between
Gen1 (2.5 Gbps) and Gen2 (5 Gbps) is achieved by changing the transceiver datapath
clock frequency between 250 MHz and 500 MHz, while maintaining a constant
transceiver interface width of 16-bit.
The dedicated PCIe rateswitch circuitry performs the dynamic switch between the
Gen1 (2.5 Gbps) and Gen2 (5 Gbps) signaling rate. The PCIe rateswitch circuitry
consists of:
■
■
Change the transceiver datapath clock frequency, keeping the transceiver interface
width constant
Change the transceiver interface width between 8 bit and 16 bit, keeping the
transceiver clock frequency constant
PCIe rateswitch controller
PCIe clock switch circuitry
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rate
Stratix IV Device Handbook Volume 2: Transceivers
1–141