R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 10

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.7
3.8
3.9
3.10 Usage Notes ...................................................................................................................... 32
Section 4 Instruction Features
4.1
4.2
4.3
Section 5 Instruction Set
5.1
Section 6 Instruction Descriptions
6.1
6.2
6.3
Rev. 3.00 Jul 08, 2005 page viii of xiv
3.6.1
3.6.2
3.6.3
Instruction Exceptions ...................................................................................................... 27
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
Cases in Which Exceptions Are Not Accepted................................................................. 30
Stack Status after Exception Handling.............................................................................. 31
3.10.1 Stack Pointer (SP) Value ..................................................................................... 32
3.10.2 Vector Base Register (VBR) Value ..................................................................... 32
3.10.3 Address Errors Occurring in Address Error Exception Handling Stacking......... 32
RISC-Type Instruction Set................................................................................................ 33
Addressing Modes ............................................................................................................ 37
Instruction Format............................................................................................................. 41
Instruction Set by Classification ....................................................................................... 47
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
Overview of New Instructions .......................................................................................... 71
Format of Instruction Descriptions ................................................................................... 75
New Instructions ............................................................................................................... 88
6.3.1
6.3.2
6.3.3
Interrupt Sources.................................................................................................. 25
Interrupt Priority .................................................................................................. 25
Interrupt Exception Handling .............................................................................. 26
Types of Instruction Exception............................................................................ 27
Trap Instruction ................................................................................................... 28
Slot Illegal Instructions........................................................................................ 28
General Illegal Instructions.................................................................................. 29
Integer Division Instructions ............................................................................... 29
Floating-Point Operation Instructions.................................................................. 29
Data Transfer Instructions ................................................................................... 54
Arithmetic Operation Instructions ....................................................................... 58
Logic Operation Instructions ............................................................................... 61
Shift Instructions.................................................................................................. 62
Branch Instructions.............................................................................................. 63
System Control Instructions................................................................................. 64
Floating-Point Instructions .................................................................................. 66
FPU-Related CPU Instructions............................................................................ 68
Bit Manipulation Instructions .............................................................................. 69
BAND......... Bit AND ...................................... Bit Manipulation Instruction ... 88
BANDNOT Bit ANDNOT .............................. Bit Manipulation Instruction ... 90
BCLR ......... Bit CLeaR .................................... Bit Manipulation Instruction ... 92
.................................................................................................... 47
......................................................................................... 33
.................................................................................. 71