R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 183

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.7
Format
BRA
Description
Branches unconditionally after executing the instruction following this BRA instruction. The
branch destination is an address specified by PC + displacement. However, in this case it is used
for address calculation. The PC is the address 4 bytes after this instruction. The 12-bit
displacement is sign-extended and doubled. Consequently, the relative interval from the branch
destination is –4096 to +4094 bytes. If the displacement is too short to reach the branch
destination, this instruction must be changed to the JMP instruction. Here, a MOV instruction
must be used to transfer the destination address to a register.
Note
Since this is a delayed branch instruction, the instruction after BRA is executed before branching.
No interrupts and address errors are accepted between this instruction and the next instruction. If
the next instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation
BRA(long d)
{
}
unsigned long temp;
long disp;
if ((d&0x800)==0) disp=(0x00000FFF & (long) d);
else disp=(0xFFFFF000 | (long) d);
temp=PC;
PC=PC+(disp<<1);
Delay_Slot(temp+2);
label
BRA
Unconditional Branch
disp × 2 + PC → PC
Abstract
/* BRA disp */
BRAnch
Code
1010dddddddddddd
Rev. 3.00 Jul 08, 2005 page 167 of 484
Section 6 Instruction Descriptions
Branch Instruction
Delayed Branch Instruction
REJ09B0051-0300
Cycle
2
T Bit
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