R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 337

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.5.20
Description
This instruction loads the source operand into FPU system registers FPUL and FPSCR.
Operation
Format
LDS
LDS.L @Rm+,FPUL
LDS
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 1
#define FPSCR_MASK 0x003FFFFF
LDSFPUL(int m, int *FPUL)
{
}
LDSMFPUL(int m, int *FPUL)
{
}
LDSFPSCR(int
{
}
LDSMFPSCR(int
{
Rm,FPUL
Rm,FPSCR
*FPUL=R[m];
PC+=2;
*FPUL=Read_Long(R[m]);
R[m]+=4;
PC+=2;
FPSCR=R[m] & FPSCR_MASK;
PC+=2;
LDS
Load to FPU
System Register
m)
m)
Abstract
Rm → FPUL
(Rm) → FPUL, Rm+4 → Rm
Rm → FPSCR
LoaD to FPU System
register
/* LDS Rm,FPSCR
/* LDS.L @Rm+,FPSCR
/* LDS Rm,FPUL
/* LDS.L @Rm+,FPUL
Code
0100mmmm01011010 1
0100mmmm01010110 1
0100mmmm01101010 1
*/
Rev. 3.00 Jul 08, 2005 page 321 of 484
Section 6 Instruction Descriptions
*/
*/
System Control Instruction
*/
Cycle
REJ09B0051-0300
T Bit
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